View PE64101MLAA-Z_4949921.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

page 1 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. product description the pe64101 is a dune?-enhanced digitally tunable capacitor (dtc) based on peregrine?s ultracmos ? technology. dtc products provide a monolithically integrated impedance tuning solution for demanding rf applications. they also offer a cost-effective tunable capacitor with excellent linearity and esd performance. this highly versatile product can be mounted in series or shunt configuration and is controlled by a 3-wire (spi compatible) serial interface. high esd rating of 2 kv hbm on all ports making this the ultimate in integration and ruggedness. the dtc is offered in a standard 12- lead 2.0 x 2.0 x 0.55 mm qfn package. peregrine?s dune? technology enhancements deliver high linearity and exceptional harmonics performance. it is an innovative feature of the ultracmos ? process, providing performance superior to gaas with the economy and integration of conventional cmos. figure 1. functional block diagram 71-0066-01 figure 2. package type 12-lead 2 x 2 x 0.55 mm qfn features ?? 3-wire (spi compatible) 8-bit serial interface with built-in bias voltage generation and stand-by mode for reduced power consumption ?? dune?-enhanced ultracmos ? device ?? 5-bit 32-state digitally tunable capacitor ?? c = 1.38 ? 5.90 pf (4.3:1 tuning ratio) in discrete 146 ff steps ?? rf power handling (up to 26 dbm, 6 v pk rf) and high linearity ?? high quality factor ?? wide power supply range (2.3 to 3.6v) and low current consumption (typ. i dd = 30 a @ 2.8v) ?? optimized for shunt configuration, but can also be used in series configuration ?? excellent 2 kv hbm esd tolerance on all pins ?? applications include: ?? antenna tuning ?? tunable filters ?? phase shifters ?? impedance matching product specification ultracmos ? digitally tunable capacitor (dtc) 100 - 3000 mhz pe64101
product specification pe64101 page 2 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions table 1. electrical specifications @ 25c, v dd = 2.8v parameter configuration condition min typ max units operating frequency range 7 both 100 3000 mhz minimum capacitance shunt 6 state = 00000, 100 mhz (rf+ to grounded rf-) -10% 1.38 +10% pf maximum capacitance shunt 6 state = 11111, 100 mhz (rf+ to grounded rf-) -10% 5.90 +10% pf tuning ratio shunt 6 c max /c min , 100 mhz 4.3:1 step size shunt 6 5 bits (32 states), constant step size (100 mhz) 0.146 pf quality factor (c min ) 1 shunt 6 470 - 582 mhz with l s removed 698 - 960 mhz, with l s removed 1710 - 2170 mhz, with l s removed 50 50 30 quality factor (c max ) 1 shunt 6 470 - 582 mhz with l s removed 698 - 960 mhz, with l s removed 1710 - 2170 mhz, with l s removed 50 25 10 self resonant frequency shunt 7 state 00000 state 11111 5.5 2.5 ghz harmonics (2 fo and 3 fo ) 4 shunt 6 470 to 582 mhz, pin +26 dbm, 50 ? 698 to 915 mhz, pin +26 dbm, 50 ? 1710 to 1910 mhz, pin +26 dbm, 50 ? -36 -36 -36 dbm dbm dbm series 5 470 to 582 mhz, pin +20 dbm, 50 ? 698 to 915 mhz, pin +20 dbm, 50 ? 1710 to 1910 mhz, pin +20 dbm, 50 ? -36 -36 -36 dbm dbm dbm 3rd order intercept point shunt 6 iip3 = (pblocker + 2*ptx - [imd3]) / 2, where imd3 = -95 dbm, ptx = +20 dbm and pblocker = -15 dbm 60 dbm switching time 2, 3 shunt 6 state change to 10/90% delta capacitance between any two states 2 10 s start-up time 2 shunt 6 time from v dd within specification to all performances within specification 5 20 s wake-up time 2, 3 shunt 6 state change from standby mode to rf state to all performances within specification 5 20 s note: 1. q for a shunt dtc based on a series rlc equivalent circuit q = x c / r = (x-x l )/r, where x = x l + x c , x l = 2*pi*f*l, x c = -1 / (2*pi*f*c), which is equal to remo ving the effect of parasitic inductance l s 2. dc path to ground at rf+ and rf? must be provided to achieve specified performance 3. state change activated on falling edge of sen following data word 4. between 50 ? ports in series or shunt configuration using a pulsed rf input with 4620 vs period, 50% duty cycle, measured per 3gppts45.005 5. in series configuration the greater rf pow er or higher rf voltage should be applied to rf+ 6. rf - should be connected to ground 7. dtc operation above srf is possible
product specification pe64101 page 3 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. table 3. operating ranges 1 parameter symbol min typ max units v dd supply voltage v dd 2.3 2.8 3.6 v i dd power supply current (normal mode) 6 i dd 30 75 a i dd power supply current (standby mode) 6 i dd 20 45 a control voltage high v ih 1.2 3.1 v control voltage low v il 0 0.2 v peak operating rf voltage 5 v p to v m v p to rfgnd v m to rfgnd 6 6 6 v pk v pk v pk rf input power (50 ? ) 3, 4, 5 shunt series +26 +20 dbm dbm input control current i ctl 1 10 a operating temperature range t op -40 +85 c storage temperature range t st -65 +150 c table 4. absolute maximum ratings symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v esd esd voltage (hbm, mil_std 883 method 3015.7) 2000 v v esd esd voltage (mm, jedec jesd22-a115-a) 100 v v i voltage on any dc input -0.3 4.0 v notes: 1. operation should be restricted to the limits in the operating ranges table 2. the dtc is active when stby is low (set to 0) and in low-current stand-by mode when high (set to 1) 3. maximum cw power available from a 50 ? source in shunt configuration 4. maximum cw power available from a 50 ? source in series configuration 5. rf+ to rf- and rf+ and/or rf- to ground. cannot exceed 6 v pk or max rf input power (which ever occurs first) 6. i dd current typical value is based on v dd = 2.8v. max i dd is based on v dd = 3.6v exceeding absolute maximum ratings may cause permanent damage. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. figure 3. pin configuration (top view) moisture sensitivity level the moisture sensitivity level rating for the pe64101 in the 12-lead 2 x 2 qfn package is msl1. table 2. pin descriptions pin # pin name description 1 sen serial enable 2 gnd digital and rf ground 3 sclk serial interface clock input 4 vdd power voltage 5 gnd digital and rf ground 6 rf- negative rf port 1 7 rf- negative rf port 1 8 gnd digital and rf ground 3 9 rf+ positive rf port 2 10 rf+ positive rf port 2 13 gnd digital and rf ground 3 12 sdat serial interface data input 11 gnd digital and rf ground notes: 1. pins 6 and 7 must be tied together on pcb board to reduce inductance 2. pins 9 and 10 must be tied together on pcb board to reduce inductance 3. pin 2, 5, 8, 11 and 13 mu st be connected together on pcb sen 6 7 8 1 2 3 gnd sclk rf+ gnd rf- 13 gnd 12 11 10 9 4 5 6 8 7 1 2 3 pin 1
product specification pe64101 page 4 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions figure 6. measured step size vs state (frequency) figure 5. measured shunt s 11 (major states) performance plots @ 25c and 2.8v unless otherwise specified figure 8. measured shunt c vs frequency (major states) figure 9. measured series s 21 vs frequency (major states) figure 4. measured shunt c (@ 100 mhz) vs state (temperature) 0 0.5 1 1.5 2 2.5 3 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (ghz) db(s21) measured series s21 vs. frequency (major states) c0 c1 c2 c4 c8 c16 c31 figure 7. measured series s 11 /s 22 (major states) 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 state capacitance(pf) measured shunt c (@ 100 mhz) vs. state 5 10 15 20 25 30 50 100 150 200 state step size (ff) measured step size vs. state (frequency) 100 mhz 470 mhz 582 mhz 862 mhz measured series s11/s22 (major states) frequency(.3 - 3000 mhz) s11 c0 s22 c0 s11 c1 s22 c1 s11 c2 s22 c2 s11 c4 s22 c4 s11 c8 s22 c8 s11 c16 s22 c16 s11 c31 s22 c31
product specification pe64101 page 5 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. figure 11. measured 2-port shunt s21 vs frequency (major states) figure 10. measured shunt q vs frequency (major states) figure 12. measured self resonance frequency vs state 0 2 4 6 8 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (ghz) db(s21) measured 2-port shunt s21 vs. frequency (major states) c0 c1 c2 c4 c8 c16 c31 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 6 measured self resonance frequency vs. state state [0..31] self resonance frequency (ghz) figure 13. measured shunt q vs state 5 10 15 20 25 30 0 20 40 60 80 100 120 140 160 state q measured q vs. state 100 mhz 470 mhz 698 mhz 1710 mhz
product specification pe64101 page 6 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions serial interface operation and sharing the pe64101 is controlled by a three wire spi- compatible interface. as shown in figure 14 , the serial master initiates the start of a telegram by driving the sen (serial enable) line high. each bit of the 8-bit telegram is clocked in on the rising edge of the scl (serial clock) line. sda bits are clocked by most significant bit (msb) first, as shown in table 5 and figure 14 . transactions on sda (serial data) are allowed on the falling edge of scl. the dtc activates the data on the falling edge of sen. the dtc does not count how many bits are clocked and only maintains the last 8 bits it received. more than 1 dtc can be controlled by one interface by utilizing a dedicated enable (sen) line for each dtc. sda, scl, and v dd lines may be shared as shown in figure 15 . dedicated sen lines act as a chip select such that each dtc will only respond to serial transactions intended for them. this makes each dtc change states sequentially as they are programmed. alternatively, a dedicated sda line with common sen can be used. this allows all dtcs to change states simultaneously, but requires all dtcs to be programmed even if the state is not changed. figure 14. serial interface timing diagram (oscilloscope view) b5 b6 t r t dhd t dsu 1/f clk b7 b0 b4 b3 b2 b1 d m-1 <7:0> d m <7:0> b0 d m-2 <7:0> t epw t f t esu t ehd sen scl sda dtc data
product specification pe64101 page 7 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. table 5. 6-bit serial programming register map table 6. serial interface ac characteristics ? 2.3v < v dd < 3.6v, -40 c < t a < +85 c, unless otherwise specified symbol parameter min max unit f clk serial clock frequency 26 mhz t r scl, sda, sen rise time 6.5 ns t f scl, sda, sen fall time 6.5 ns t esu sen rising edge to scl rising edge 19.2 ns t ehd scl rising edge to sen falling edge 19.2 ns t dsu sda valid to scl rising edge 13.2 ns t dhd sda valid after scl rising edge 13.2 ns t eow sen falling edge to sen rising edge 38.4 ns b4 b3 b2 b1 b0 d4 d3 d2 d1 d0 b5 stb 1 b7 b6 0 0 msb (first in) lsb (last in) note: 1. the dtc is active when low (set to 0) and in low-current stand-by mode when high (set to 1) figure 15. recommended bus sharing scl sda v dd gnd dgnd rf- rf+ scl sda v dd sen gnd dgnd rf- rf+ scl sda v dd dtc 1 sen sen2 sen1 dtc 2
product specification pe64101 page 8 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions equivalent circuit model description the dtc equivalent circuit model includes all parasitic elements and is accurate in both series and shunt configurations, reflecting physical circuit behavior accurately and providing very close correlation to measured data. it can easily be used in circuit simulation programs. simple equations are provided for the state dependent parameters. the tuning core capacitance c s represents capacitance between rf+ and rf- ports. it is linearly proportional to state (0 to 31 in decimal) in a discrete fashion. the series tuning ratio is defined as c smax /c smin . c p1 and c p2 represent the circuit and package parasitics from rf ports to gnd. in shunt configuration the total capacitance of the dtc is higher due to parallel combination of c p and c s . in series configuration, c s and c p do not add in parallel and the dtc appears as an impedance transformation network. parasitic inductance due to circuit and package is modeled as l s and causes the apparent capacitance of the dtc to increase with frequency until it reaches self resonant frequency (srf). the value of srf depends on state and is approximately inversely proportional to the square root of capacitance. the overall dissipative losses of the dtc are modeled by r s , r p1 and r p2 resistors. the parameter r s represents the equivalent series resistance (esr) of the tuning core and is dependent on state. r p1 and r p2 represent losses due to the parasitic and biasing networks. figure 16. equivalent circuit model schematic table 7. equivalent circuit model parameters variable equation (state = 0, 1, 2?31) unit c s 0.148*state + 0.97 pf r s 30/(state+30/(state+0.4)) + 0.4 ? c p1 -0.0022*state + 0.4005 pf c p2 0.0026*state + 0.5092 pf r p1 4 ? r p2 22000 + 6*(state)^3 ? l s 0.4 nh table 8. maximum operating rf voltage condition limit v p to v m 6 v pk v p to rfgnd 6 v pk v m to rfgnd 6 v pk
product specification pe64101 page 9 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. table 9. equivalent circuit data state dtc core parasitic elements binary decimal cs [pf] rs [ ? ] cp1 [pf] cp2 [pf] rp2 [k ? ] ls [nh] rp1 [ ? ] 00000 0 0.97 0.80 0.40 0.51 22.0 0.40 00001 1 1.12 1.73 0.40 0.51 22.0 00010 2 1.27 2.41 0.40 0.51 22.0 00011 3 1.41 2.81 0.39 0.52 22.2 00100 4 1.56 2.98 0.39 0.52 22.4 00101 5 1.71 3.00 0.39 0.52 22.8 00110 6 1.86 2.92 0.39 0.52 23.3 00111 7 2.01 2.81 0.39 0.53 24.1 01000 8 2.15 2.68 0.38 0.53 25.1 01001 9 2.30 2.54 0.38 0.53 26.4 01010 10 2.45 2.42 0.38 0.54 28.0 01011 11 2.60 2.29 0.38 0.54 30.0 01100 12 2.75 2.18 0.37 0.54 32.4 01101 13 2.89 2.08 0.37 0.54 35.2 01110 14 3.04 1.99 0.37 0.55 38.5 01111 15 3.19 1.90 0.37 0.55 42.3 10000 16 3.34 1.83 0.37 0.55 46.6 10001 17 3.49 1.76 0.36 0.55 51.5 10010 18 3.63 1.69 0.36 0.56 57.0 10011 19 3.78 1.63 0.36 0.56 63.2 10100 20 3.93 1.58 0.36 0.56 70.0 10101 21 4.08 1.53 0.35 0.56 77.6 10110 22 4.23 1.48 0.35 0.57 85.9 10111 23 4.37 1.44 0.35 0.57 95.0 11000 24 4.52 1.40 0.35 0.57 104.9 11001 25 4.67 1.36 0.35 0.57 115.8 11010 26 4.82 1.33 0.34 0.58 127.4 11011 27 4.97 1.30 0.34 0.58 140.1 11100 28 5.11 1.27 0.34 0.58 153.7 11101 29 5.26 1.24 0.34 0.58 168.3 11110 30 5.41 1.21 0.33 0.59 184.0 11111 31 5.56 1.19 0.33 0.59 200.7 4.0
product specification pe64101 page 10 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions figure 17. evaluation board layout 101-0700 evaluation board the 101-0700 evaluation board (evb) was designed for accurate measurement of the dtc impedance and loss. two configurations are available: 1 port shunt (j3) and 2 port shunt (j4, j5). three calibration standards are provided. the open (j2) and short (j1) standards (104 ps delay) are used for performing port extensions and accounting for electrical length and transmission line loss. the thru (j9, j10) standard can be used to estimate pcb transmission line losses for scalar de-embedding of the 2 port shunt configuration (j4, j5). the board consists of a 4 layer stack with 2 outer layers made of rogers 4350b ( r = 3.48) and 2 inner layers of fr4 ( r = 4.80). the total thickness of this board is 62 mils (1.57 mm). the inner layers provide a ground plane for the transmission lines. each transmission line is designed using a coplanar waveguide with ground plane (cpwg) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.036 mm).
product specification pe64101 page 11 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. figure 18. evaluation board schematic 102-0833 short 1portshunt 2portshunt j2 sma conn tp4 j9 sma conn j10 sma conn j1 sma conn tp5 j3 sma conn c3 100pf 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j8 14 pin header j5 sma conn c7 100pf 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j11 14 pin header r3 dni r1 dni r2 dni r4 dni c9 100pf c10 100pf c11 100pf r5 dni r6 dni r7 dni r8 dni c12 100pf c13 100pf c14 100pf r9 dni r10 dni r11 dni r12 dni r13 dni r14 dni j4 sma conn 6 rf- 7 rf- 2 gnd 4 vdd 1 sen 12 sdat 10 rf+ 9 rf+ 11 gnd 3 sclk 5 gnd 8 gnd 13 paddle u1 pe6410x_qfn_12l_2x2 6 rf- 7 rf- 2 gnd 4 vdd 1 sen 12 sdat 10 rf+ 9 rf+ 11 gnd 3 sclk 5 gnd 8 gnd 13 paddle u2 pe6410x_qfn_12l_2x2 open thru scl sen sda vdd vdd_1 scl_1 sen_1 sda_1
product specification pe64101 page 12 of 13 ?2012 peregrine semiconductor corp. all rights reserved. document no. 70-0378-01 ultracmos ? rfic solutions figure 19. package drawing 12-lead 2 x 2 x 0.55 mm qfn figure 20. top marking specifications ppzz yww marking spec symbol package marking definition pp cr part number marking for pe64101 zz 00-99 last two digits of lot code y 0-9 last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc) ww 01-53 work week 17-0112
product specification pe64101 page 13 of 13 document no. 70-0378-01 www.psemi.com ?2012 peregrine semiconductor corp. all rights reserved. advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com . table 10. ordering information order code package description shipping method PE64101MLAA-Z 12-lead 2 x 2 x 0.55 mm qfn package part in tape and reel 3000 units/t&r ek64101-11 evaluation kit ev aluation kit 1 set/box figure 21. tape and reel specifications 12-lead 2 x 2 x 0.55 mm qfn tape feed direction device orientation in tape

▲Up To Search▲

Price & Availability of PE64101MLAA-Z

	To Download PE64101MLAA-Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .